1.Low Power, Robust SRAMs for Nano- Metric Technologies
Manoj Sachdev, University of Waterloo

2.Pushing the limits of energy consumption: opportunities and challenges
Massimo Alioto, University of Siena

3.Design Methodology of GHz Processor Designs
Vidyasagar Ganesan, Senior Member technical staff at AMD

4.Large Area Digital Imaging Technology
Karim S. Karim, University of Waterloo.

Tutorial 1

Low Power, Robust SRAMs for Nano- Metric Technologies

Manoj Sachdev, University of Waterloo

Abstract

Embedded random access memories can occupy up to 80% of the total area of modern System on Chips (SoCs). Embedded SRAMs are the most popularly used due to its robustness compared to DRAMs. Owing to a number of constraints, embedded SRAMs have a significant impact on power, performance, testability and yield of complex SoCs in sub 90nm technologies. In this presentation, some of these issues will be discussed.

Tutorial Outline

1. Motivation & Introduction (15 minutes)
2. SRAM Organization and Circuits (45 minutes)
3. SRAM Power Reduction Techniques (30 minutes)
4. Low Power SRAM Architectures (30 minutes)
5. Soft Errors and Low Power SRAMs (30 minutes)
6. SRAM yield and test algorithms (30 minutes)
7. Conclusions

Biography of Speaker

Manoj Sachdev is a University Chair Professor in Electrical and Computer Engineering department at the University of Waterloo, Canada. His research interests include low power and high performance digital circuit design, mixed-signal circuit design, test and manufacturing issues of integrated circuits. He has written five books, two book chapters on integrated circuits and has contributed to more than one hundred fifty articles in conferences and journals. He received the best paper award for his paper in European Design and Test Conference, 1997 and an honorable mention award for his paper in International Test Conference, 1998. He holds more than 25 granted and pending US patents in the area of VLSI circuit design and test. He is a senior member of IEEE. He received his B.E. degree (with Honors) in electronics and communication engineering from University of Roorkee (India), and Ph.D. from Brunel University (UK). He was with Semiconductor Complex Limited, Chandigarh (India) from 1984 till 1989 where he designed CMOS Integrated Circuits. From 1989 till 1992, he worked in the ASIC division of SGS-Thomson at Agrate (Milan). From 1992 till 1998, he worked in Philips Research Laboratories, Eindhoven, where he researched on various aspects of VLSI circuit design, testing and manufacturing.

 

 

Tutorial 2

Pushing the limits of energy consumption: opportunities and challenges

Massimo Alioto, University of Siena

Tutorial Outline

The tutorial provides a survey of fresh ideas and recent techniques to design and implement minimum energy logic circuits particularly those operating in the subthreshold regime. Emphasis is given on design tradeoffs, circuit techniques, limits and challenges involved in the chip energy reduction in the foreseeable future. Innovative directions are also presented in a simple and rigorous way.
Overview: applications and practical constraints.
Device level: degradation of electrical features in subthreshold, limits, impact of variability and models.
Transistor/gate level: static and dynamic behavior of CMOS logic, energy]delay tradeoff, design techniques and constraints in cell libraries. Composition of subthreshold cell libraries. Critical parameters vs. scaling.
Microarchitecture: effect of pipelining and hardware replication on the energy delay tradeoff.
System level: harmonizing blocks with different E-D characteristic, power-down schemes.
Case studies: simple structures, arithmetic circuits, memories. Review of state of the art circuits.
New directions: voltage mode vs. current mode, asynchronous vs. synchronous schemes, fine grain body biasing, emerging technologies

Biography of Speaker

Massimo Alioto ( (M’01–SM’07) was born in Brescia, Italy, in 1972. He received the laurea degree in Electronics Engineering and the Ph.D. degree in Electrical Engineering from the University of Catania (Italy) in 1997 and 2001, respectively. In 2002, he joined the Dipartimento di Ingegneria dell’Informazione (DII) of the University of Siena as a Research Associate and in the same year as an Assistant Professor. In 2005 he was appointed Associate Professor of Electronics, and was engaged in the same faculty in 2006. In the summer of 2007, he was a Visiting Professor at EPFL Lausanne (Switzerland). Since 2001 he has been teaching undergraduate and graduate courses on advanced VLSI digital design, microelectronics and basic electronics. He has authored or co-authored more than 100 journals (35+) and conference papers. He is co-author of the book Model and Design of Bipolar and MOS Current Mode Logic: CML, ECL and SCL Digital Circuits (Springer, 2005). His primary research interests include the modeling and the optimized design of CMOS high performance, low power and ultra low power digital circuits, arithmetic and cryptographic circuits, interconnect modeling, design/modeling for variability tolerant and low leakage VLSI circuits, circuit techniques for emerging technologies. He is the director of the Electronics Lab at University of Siena (site of Arezzo). Prof. Alioto is an IEEE Senior Member and a member of the HiPEAC Network of Excellence. He has served as a member of various conference technical or program committees (ISCAS, PATMOS) and Track Chair (ICECS). He is also member of the VLSI Systems and Applications Technical Committee of the IEEE Circuits and Systems Society, and Associate Editor of the journal Integration – The VLSI journal (Elsevier)

 

 

Tutorial 3

Design Methodology of GHz Processor Designs

Vidyasagar Ganesan, Senior Member technical staff at AMD

Abstract

Microprocessor innovation is at crossroads, Relentless push towards frequency as a single vector has imposed challenging design constraints and cost. Designing a multi-Giga Hertz Processor in nm technology presents a number of significant challenges for power, clocking and chip integration. This tutorial describes the physical design and methodology considerations to overcome these challenges and ensure predictable design convergence.

Tutorial Outline

Processor description: Processor Evolution and challenges.
Processor Design Flow: How we achieve predictable design convergence.
Timing Closure: Clocking considerations for GHz frequency, Design for variation
Power Considerations: Low Power methodology design considerations
Chip Integration: Chip Integration challenges, Repeater insertion methodology,Power/Clock distribution analysis
Summary & conclusion

Biography of Speaker

Vidyasagar Ganesan , has over 16 years of experience in overall processor development (X86, Sparc and ARM based) and has held Senior technical management positions at AMD, Sun Microsystems, Texas Instruments. At AMD he led the Soc Implementation for the 45nm Quad core Processor "Shanghai". Vidyasagar, interests are in ASIC/CPU Design Methodology/Development and Process technology and has published over 15 papers/patents filed in these areas. He has also served as a Session Chair & TPC for VLSI 05 and VLSI 08 conference and has given tutorials at number of symposiums.

 

Tutorial 4

Large Area Digital Imaging Technology

Karim S. Karim, University of Waterloo

Abstract

This tutorial covers major aspects of the design and fabrication of emerging active matrix digital imaging circuits and X-ray detectors used in digital radiography (DR). The course provides an understanding of the scientific principles, physics and engineering technology that provide the basis by which images are acquired in digital imaging.

Tutorial Outcomes

1.Refresh your knowledge on X-ray interaction with matter
2.Learn about radiographic imaging materials and methods including phosphors (CsI) and direct X-ray converters (selenium)
3.Understand the physics of imaging devices used in active matrix flat panel imagers (amorphous silicon MIS, Schottky, pin photodiodes, and thin film transistors)
4.Examine passive pixel sensor circuit designs and array architectures and extract performance metrics including frame rate and input referred electronic noise
5.Become aware of challenges and emerging technologies (PbO, HgI2 direct detection materials, avalanche selenium, amplified pixels in amorphous and poly-Si technology)

Intended Audience

This course is designed for anyone who wants to extend their understanding of digital imaging and commercially available state-of-the-art large area active matrix flat panel imagers. It is of value to engineers, physicists, computer scientists and others involved in the design, production, evaluation or purchase of components for digital imaging equipment.

Biography of Speaker

Karim S. Karim received his PhD (2002) from the University of Waterloo. He joined Simon Fraser University in 2003 where he was an assistant professor from 2003 to 2007. He is currently an assistant professor in the Department of Electrical and Computer Engineering at the University of Waterloo and directs the Silicon Thin-film Applied Research (STAR), a research group he established in 2003 that currently consists of 6 PhD and 4 MASc students. His research interests span large-area circuit, device and process development in amorphous and crystalline silicon semiconductor technologies for medical imaging applications. Dr. Karim has been involved with the design of large area active matrix digital x-ray imagers since 1999 and has more than 10 patents and 90 publications to date in this field. He has been awarded the CAGS/UMI award for the best doctoral thesis in science and medicine in Canada, the NSERC Doctoral Prize and the Douglas Colton medal for research excellence in microelectronics applied to medical imaging for his work on amorphous silicon pixel amplifier technology for digital fluoroscopy. He was awarded the Michael Merickel Best Student Paper Award in 2001, the Cum Laude Poster Award in 2004 and his graduate students have received honorable mention poster awards for papers co-authored in 2006, 2007 and 2008. He is a member of the SPIE, IEEE, AAPM and ECS societies and is registered as a Professional Engineer (PEng) in Canada.